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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-27 07:58:10 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-05-27 08:00:00 +0000 |
| commit | 6228b10c9f354afaa009491b061583e8a686fbd8 (patch) | |
| tree | 21edb9a0d68cbcc7a9029b8428e5aa7ed6cb92d3 /tests | |
| parent | e50e4ee285e8c3989cdf983640451aebd7e6e152 (diff) | |
| download | yosys-6228b10c9f354afaa009491b061583e8a686fbd8.tar.gz yosys-6228b10c9f354afaa009491b061583e8a686fbd8.tar.bz2 yosys-6228b10c9f354afaa009491b061583e8a686fbd8.zip | |
printattrs: Add test.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/printattr.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys new file mode 100644 index 000000000..afc6d8eb6 --- /dev/null +++ b/tests/various/printattr.ys @@ -0,0 +1,14 @@ +logger -expect log ".*cells_not_processed=[01]* .*" 1 +logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1 +read_verilog <<EOT +module mux2(a, b, s, y); + input a, b, s; + output y; + + wire s_n = ~s; + wire t0 = s & a; + wire t1 = s_n & b; + assign y = t0 | t1; +endmodule +EOT +printattrs |