diff options
| author | Clifford Wolf <clifford@clifford.at> | 2019-03-19 14:08:57 +0100 | 
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-19 14:08:57 +0100 | 
| commit | 61f37706f93042c2d1f093dd9bfa717390911eb3 (patch) | |
| tree | e24fec68370fda597f489be075e4696d44f465f5 /tests | |
| parent | 90bce0415622a3d7a64bca5914a0fb3abdd3cc5c (diff) | |
| parent | a5f4b836376e1457847da4946c1e12d2d41dc4f4 (diff) | |
| download | yosys-61f37706f93042c2d1f093dd9bfa717390911eb3.tar.gz yosys-61f37706f93042c2d1f093dd9bfa717390911eb3.tar.bz2 yosys-61f37706f93042c2d1f093dd9bfa717390911eb3.zip  | |
Merge pull request #884 from zachjs/master
fix local name resolution in prefix constructs
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/simple/generate.v | 56 | 
1 files changed, 56 insertions, 0 deletions
diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 24eb4462c..3c55682cb 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -90,5 +90,61 @@ generate  		endcase  	end  endgenerate +endmodule + +// ------------------------------------------ + +module gen_test4(a, b); + +input [3:0] a; +output [3:0] b; + +genvar i; +generate +	for (i=0; i < 3; i=i+1) begin : foo +		localparam PREV = i - 1; +		wire temp; +		if (i == 0) +			assign temp = a[0]; +		else +			assign temp = foo[PREV].temp & a[i]; +		assign b[i] = temp; +	end +endgenerate +endmodule + +// ------------------------------------------ + +module gen_test5(input_bits, out); + +parameter WIDTH = 256; +parameter CHUNK = 4; +input [WIDTH-1:0] input_bits; +output out; + +genvar step, i, j; +generate +	for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps +		localparam PREV = step / CHUNK; +		localparam DIM = WIDTH / step; +		for (i = 0; i < DIM; i = i + 1) begin : outer +			localparam LAST_START = i * CHUNK; +			for (j = 0; j < CHUNK; j = j + 1) begin : inner +				wire temp; +				if (step == 1) +					assign temp = input_bits[i]; +				else if (j == 0) +					assign temp = steps[PREV].outer[LAST_START].val; +				else +					assign temp +						= steps[step].outer[i].inner[j-1].temp +						& steps[PREV].outer[LAST_START + j].val; +			end +			wire val; +			assign val = steps[step].outer[i].inner[CHUNK - 1].temp; +		end +	end +endgenerate +assign out = steps[WIDTH].outer[0].val;  endmodule  | 
