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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-29 10:10:09 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-29 10:10:09 +0200 |
| commit | 5b5fe76966b44ebc35e0087072c1df2c2bba044b (patch) | |
| tree | e3f5d264d380cf7f0b29892205be6412a940188e /tests | |
| parent | 4bc1e1d1f1d3f27b3e437591255a38ab647f0453 (diff) | |
| download | yosys-5b5fe76966b44ebc35e0087072c1df2c2bba044b.tar.gz yosys-5b5fe76966b44ebc35e0087072c1df2c2bba044b.tar.bz2 yosys-5b5fe76966b44ebc35e0087072c1df2c2bba044b.zip | |
Add test for bug 3462
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/bug3462.ys | 12 | ||||
| -rw-r--r-- | tests/various/sub.v | 3 |
2 files changed, 15 insertions, 0 deletions
diff --git a/tests/various/bug3462.ys b/tests/various/bug3462.ys new file mode 100644 index 000000000..c85dc9470 --- /dev/null +++ b/tests/various/bug3462.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module top(); + wire array[0:0]; + wire out; + sub #(.d(1)) inst( + .in(array[0]), + .out(out) + ); +endmodule +EOT + +hierarchy -top top -libdir . diff --git a/tests/various/sub.v b/tests/various/sub.v new file mode 100644 index 000000000..63422ca5c --- /dev/null +++ b/tests/various/sub.v @@ -0,0 +1,3 @@ +module sub #(parameter d=1) (input in, output out); + assign out = in; +endmodule |