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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 16:01:36 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 16:01:36 +0300 |
| commit | 53912ad649d6e9f447b9e4037255606783a0cf51 (patch) | |
| tree | afe83ac171c16e7edcadeb9ded445a940dcf3972 /tests | |
| parent | 17c92dc679458a9ffabd76e2ce8e2491bd249110 (diff) | |
| download | yosys-53912ad649d6e9f447b9e4037255606783a0cf51.tar.gz yosys-53912ad649d6e9f447b9e4037255606783a0cf51.tar.bz2 yosys-53912ad649d6e9f447b9e4037255606783a0cf51.zip | |
macc test fix
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/macc.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index d65c31b73..fe5b5f662 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -5,6 +5,6 @@ equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 38 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY +select -assert-count 3 t:SB_CARRY select -assert-count 7 t:SB_DFFSR select -assert-none t:SB_LUT4 t:SB_CARRY t:SB_DFFSR %% t:* %D |