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| author | Eddie Hung <eddie@fpgeh.com> | 2020-06-03 17:35:46 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-03 17:35:46 -0700 |
| commit | 45cd323055270ff414419ddf8a9b5d08f40628b5 (patch) | |
| tree | dca3058ce1f8bfa3a030716d40abf662d6733c0f /tests | |
| parent | 46ed0db2ec883a4ce330c81f321511e36e35c0b3 (diff) | |
| parent | 8a11019d382f3eb5a8d95ce64511a1dcbbe2acfe (diff) | |
| download | yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.gz yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.tar.bz2 yosys-45cd323055270ff414419ddf8a9b5d08f40628b5.zip | |
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes
abc9: fixes around handling combinatorial loops
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ecp5/latches_abc9.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/arch/ecp5/latches_abc9.ys b/tests/arch/ecp5/latches_abc9.ys new file mode 100644 index 000000000..4daf04050 --- /dev/null +++ b/tests/arch/ecp5/latches_abc9.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT +module top(input e, d, output q); +reg l; +always @* + if (e) + l = ~d; +assign q = ~l; +endmodule +EOT +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 -abc9 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT4 %% t:* %D |