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authorKrystalDelusion <krystinedawn@yosyshq.com>2022-07-25 10:12:30 +1200
committerKrystalDelusion <krystinedawn@yosyshq.com>2023-02-21 05:23:16 +1300
commit445a801a8587d75d3f0767cf9ba15776f50c5287 (patch)
tree2ceeab7bb3287d23ce798d8d74217a325d754b4b /tests
parent51c2d476c2209b3dad9e0a0199648274b5c3ea82 (diff)
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bug3205.ys removed
Made redundant by TDP test(s) in memories.ys
Diffstat (limited to 'tests')
-rw-r--r--tests/arch/ecp5/bug3205.ys57
1 files changed, 0 insertions, 57 deletions
diff --git a/tests/arch/ecp5/bug3205.ys b/tests/arch/ecp5/bug3205.ys
deleted file mode 100644
index f2e936530..000000000
--- a/tests/arch/ecp5/bug3205.ys
+++ /dev/null
@@ -1,57 +0,0 @@
-read_verilog <<EOT
-`timescale 100fs/100fs
-module TopEntity_topEntity_trueDualPortBlockRamWrapper
- ( // Inputs
- input clkA // clock
- , input enA
- , input weA
- , input [15:0] addrA
- , input [23:0] datA
- , input clkB // clock
- , input enB
- , input weB
- , input [15:0] addrB
- , input [23:0] datB
-
- // Outputs
- , output wire [47:0] result
- );
-
-
- // trueDualPortBlockRam begin
- // Shared memory
- // 24*64k = 1.5M = 96*DP16KD
- reg [24-1:0] mem [65536-1:0];
-
- reg [23:0] data_slow;
- reg [23:0] data_fast;
-
- // Port A
- always @(posedge clkA) begin
- if(enA) begin
- data_slow <= mem[addrA];
- if(weA) begin
- data_slow <= datA;
- mem[addrA] <= datA;
- end
- end
- end
-
- // Port B
- always @(posedge clkB) begin
- if(enB) begin
- data_fast <= mem[addrB];
- if(weB) begin
- data_fast <= datB;
- mem[addrB] <= datB;
- end
- end
- end
-
- assign result = {data_slow, data_fast};
-
- // end trueDualPortBlockRam
-endmodule
-EOT
-synth_ecp5 -top TopEntity_topEntity_trueDualPortBlockRamWrapper
-select -assert-count 96 t:DP16KD