Merge pull request #1778 from rswarbrick/sv-defines

Add support for SystemVerilog-style `define to Verilog frontend

4 files changed, 50 insertions, 0 deletions

diff --git a/tests/various/sv_defines.ys b/tests/various/sv_defines.ys
new file mode 100644
index 000000000..8e70ee0ee
--- /dev/null
+++ b/tests/various/sv_defines.ys
@@ -0,0 +1,33 @@
+# Check that basic macro expansions do what you'd expect
+
+read_verilog <<EOT
+`define empty_arglist()                      123
+`define one_arg(x)                           123+x
+`define opt_arg(x = 1)                       123+x
+`define two_args(x, y = (1+23))              x+y
+`define nested_comma(x = {31'b0, 1'b1}, y=3) x+y
+
+module top;
+  localparam a = `empty_arglist();
+  localparam b = `one_arg(10);
+  localparam c = `opt_arg(10);
+  localparam d = `opt_arg();
+  localparam e = `two_args(1,2);
+  localparam f = `two_args(1);
+  localparam g = `nested_comma(1, 2);
+  localparam h = `nested_comma({31'b0, (1'b0)});
+  localparam i = `nested_comma(, 1);
+
+  generate
+    if (a != 123) $error("a bad");
+    if (b != 133) $error("b bad");
+    if (c != 133) $error("c bad");
+    if (d != 124) $error("d bad");
+    if (e != 3)   $error("e bad");
+    if (f != 25)  $error("f bad");
+    if (g != 3)   $error("g bad");
+    if (h != 3)   $error("h bad");
+    if (i != 2)   $error("i bad");
+  endgenerate
+endmodule
+EOT
diff --git a/tests/various/sv_defines_dup.ys b/tests/various/sv_defines_dup.ys
new file mode 100644
index 000000000..38418ba8f
--- /dev/null
+++ b/tests/various/sv_defines_dup.ys
@@ -0,0 +1,5 @@
+# Check for duplicate arguments
+logger -expect error "Duplicate macro arguments with name `x'" 1
+read_verilog <<EOT
+`define duplicate_arg(x, x)
+EOT
diff --git a/tests/various/sv_defines_mismatch.ys b/tests/various/sv_defines_mismatch.ys
new file mode 100644
index 000000000..ab6e899de
--- /dev/null
+++ b/tests/various/sv_defines_mismatch.ys
@@ -0,0 +1,5 @@
+# Check that we spot mismatched brackets
+logger -expect error "Mismatched brackets in macro argument: \[ and }." 1
+read_verilog <<EOT
+`define foo(x=[1,2})
+EOT
diff --git a/tests/various/sv_defines_too_few.ys b/tests/various/sv_defines_too_few.ys
new file mode 100644
index 000000000..295884809
--- /dev/null
+++ b/tests/various/sv_defines_too_few.ys
@@ -0,0 +1,7 @@
+# Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
+# arguments actually passes 1 empty argument).
+logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
+read_verilog <<EOT
+`define foo(x=1, y)
+`foo()
+EOT