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| author | luke whittlesey <luke.whittlesey@gmail.com> | 2015-05-08 15:29:51 -0400 |
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| committer | luke whittlesey <luke.whittlesey@gmail.com> | 2015-05-08 15:29:51 -0400 |
| commit | 2c1e15029786fe8a118343b7a81f681450a8ce93 (patch) | |
| tree | d86ef62ae3c058a5b30697c08ca30dfdb6f25a7d /tests | |
| parent | c0b68f4848f709034d68dbfa8697abe76b67a69e (diff) | |
| download | yosys-2c1e15029786fe8a118343b7a81f681450a8ce93.tar.gz yosys-2c1e15029786fe8a118343b7a81f681450a8ce93.tar.bz2 yosys-2c1e15029786fe8a118343b7a81f681450a8ce93.zip | |
Verilog backend for $mem cells should now be able to handle different
write-enable bits and RD_TRANSPARENT parameter settings.
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions