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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 19:40:39 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-02 19:40:39 -0700 |
| commit | 278533fe591aac14618c975e4396f885871aec54 (patch) | |
| tree | 6c78d11bb35446b6e2b0e999ca017f071dc26676 /tests | |
| parent | 62c66406ad69c4cf02c3edc843d80e0e2b05c384 (diff) | |
| parent | 265a655ef906fa0fc9ae30c1315db312e13ebd18 (diff) | |
| download | yosys-278533fe591aac14618c975e4396f885871aec54.tar.gz yosys-278533fe591aac14618c975e4396f885871aec54.tar.bz2 yosys-278533fe591aac14618c975e4396f885871aec54.zip | |
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/techmap_replace.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys new file mode 100644 index 000000000..c2f42d50b --- /dev/null +++ b/tests/techmap/techmap_replace.ys @@ -0,0 +1,18 @@ +read_verilog <<EOT +module sub(input i, output o, input j); +foobar _TECHMAP_REPLACE_(i, o, j); +wire _TECHMAP_REPLACE_.asdf = i ; +barfoo _TECHMAP_REPLACE_.blah (i, o, j); +endmodule +EOT +design -stash techmap + +read_verilog <<EOT +module top(input i, output o); +sub s0(i, o); +endmodule +EOT + +techmap -map %techmap +select -assert-any w:s0.asdf +select -assert-any c:s0.blah |