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author | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 12:34:44 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-04 12:34:44 -0700 |
commit | 0cee66e7591b6315f9e7dce91b789c1f6b53138f (patch) | |
tree | 0d1560cd13ecd61cbe53e46b1005e19132794bf9 /tests | |
parent | 3c462e5eeb5d24f5252bc1e7437f91372ec48fd0 (diff) | |
download | yosys-0cee66e7591b6315f9e7dce91b789c1f6b53138f.tar.gz yosys-0cee66e7591b6315f9e7dce91b789c1f6b53138f.tar.bz2 yosys-0cee66e7591b6315f9e7dce91b789c1f6b53138f.zip |
Add peepopt_dffmuxext tests
Diffstat (limited to 'tests')
-rw-r--r-- | tests/simple/peepopt.v | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v index 1bf427897..b4d113dba 100644 --- a/tests/simple/peepopt.v +++ b/tests/simple/peepopt.v @@ -11,3 +11,11 @@ wire [3:0] t; assign t = i * 3; assign o = t / 3; endmodule + +module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule + +module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule |