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| author | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-01 13:48:19 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2020-06-01 13:48:19 +0200 |
| commit | 0a88f002e50c0196175303068bcb3875a01d2c57 (patch) | |
| tree | 999791a4a52d234c673730292e7a725f6927c957 /tests | |
| parent | ff785cdb46d6b1ddc19d5acc21b4d1236b3adf3f (diff) | |
| download | yosys-0a88f002e50c0196175303068bcb3875a01d2c57.tar.gz yosys-0a88f002e50c0196175303068bcb3875a01d2c57.tar.bz2 yosys-0a88f002e50c0196175303068bcb3875a01d2c57.zip | |
allow range for mux test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ice40/mux.ys | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 99822391d..2b661fd6b 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -35,6 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 +select -assert-min 11 t:SB_LUT4 +select -assert-max 12 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D |