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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-09 08:33:26 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:08:38 +0200 |
| commit | 2ae7dec5300bb61a90842fefb1e846cd9f667a9e (patch) | |
| tree | 08dc91d97768a9dc657a298d87b06e31576cb06c /tests/xilinx_ug901/rams_pipeline.ys | |
| parent | 0d037bf9d8d866239de15d72dc8c5acd7ab5e5cf (diff) | |
| download | yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.tar.gz yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.tar.bz2 yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.zip | |
Add tests for Xilinx UG901 examples
Diffstat (limited to 'tests/xilinx_ug901/rams_pipeline.ys')
| -rw-r--r-- | tests/xilinx_ug901/rams_pipeline.ys | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/xilinx_ug901/rams_pipeline.ys b/tests/xilinx_ug901/rams_pipeline.ys new file mode 100644 index 000000000..7fd7c76e4 --- /dev/null +++ b/tests/xilinx_ug901/rams_pipeline.ys @@ -0,0 +1,22 @@ +read_verilog rams_pipeline.v +hierarchy -top rams_pipeline +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd rams_pipeline +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 32 t:FDRE +select -assert-count 2 t:RAMB18E1 + +select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D |