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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-09-09 08:33:26 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:08:38 +0200 |
| commit | 2ae7dec5300bb61a90842fefb1e846cd9f667a9e (patch) | |
| tree | 08dc91d97768a9dc657a298d87b06e31576cb06c /tests/xilinx_ug901/presubmult.ys | |
| parent | 0d037bf9d8d866239de15d72dc8c5acd7ab5e5cf (diff) | |
| download | yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.tar.gz yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.tar.bz2 yosys-2ae7dec5300bb61a90842fefb1e846cd9f667a9e.zip | |
Add tests for Xilinx UG901 examples
Diffstat (limited to 'tests/xilinx_ug901/presubmult.ys')
| -rw-r--r-- | tests/xilinx_ug901/presubmult.ys | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/xilinx_ug901/presubmult.ys b/tests/xilinx_ug901/presubmult.ys new file mode 100644 index 000000000..831458dec --- /dev/null +++ b/tests/xilinx_ug901/presubmult.ys @@ -0,0 +1,23 @@ +read_verilog presubmult.v +hierarchy -top presubmult +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd presubmult +#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8) +stat +select -assert-count 1 t:BUFG +select -assert-count 51 t:FDRE +select -assert-count 75 t:LUT2 +select -assert-count 10 t:LUT3 +select -assert-count 24 t:LUT4 +select -assert-count 15 t:LUT5 +select -assert-count 136 t:LUT6 +select -assert-count 24 t:MUXCY +select -assert-count 46 t:MUXF7 +select -assert-count 14 t:MUXF8 +select -assert-count 26 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D |