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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 08:06:57 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 08:06:57 +0200 |
| commit | e6ad714d20134612521e995c72e4fa06ed791dd3 (patch) | |
| tree | 38f3dc5651aa6bab8afb3217a90a7c0350ef23ae /tests/xilinx/macc.ys | |
| parent | 980df499abb63e5dfadc29b3326032b55b6dbf18 (diff) | |
| download | yosys-e6ad714d20134612521e995c72e4fa06ed791dd3.tar.gz yosys-e6ad714d20134612521e995c72e4fa06ed791dd3.tar.bz2 yosys-e6ad714d20134612521e995c72e4fa06ed791dd3.zip | |
hierarchy - proc reorder
Diffstat (limited to 'tests/xilinx/macc.ys')
| -rw-r--r-- | tests/xilinx/macc.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 417a3b21b..6e884b35a 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,8 +1,8 @@ read_verilog macc.v design -save read -proc hierarchy -top macc +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read -proc hierarchy -top macc2 +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter |