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author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:28 +0200 |
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committer | GitHub <noreply@github.com> | 2019-10-18 10:54:28 +0200 |
commit | b4d765054897f7ee388b54d907fd8ce607db2d58 (patch) | |
tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/xilinx/latches.v | |
parent | b659082e4a72209af62a19668800bb6334a437d7 (diff) | |
parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
download | yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.gz yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.tar.bz2 yosys-b4d765054897f7ee388b54d907fd8ce607db2d58.zip |
Merge branch 'master' into mmicko/efinix
Diffstat (limited to 'tests/xilinx/latches.v')
-rw-r--r-- | tests/xilinx/latches.v | 40 |
1 files changed, 3 insertions, 37 deletions
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 83bad7f35..adb5d5319 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -1,19 +1,19 @@ module latchp - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule module latchn - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule module latchsr - ( input d, en, clr, pre, output reg q ); + ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule |