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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-03-11 19:02:57 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-11 19:02:57 +0100 |
| commit | cbece4af0caebc7f04382f61492e61c84b6acbfd (patch) | |
| tree | 9de25b1d39b2e2bc0c54dde23db1b0a95ff9ad29 /tests/verilog | |
| parent | 532343dcfa3af45c1f4fe6fbda483e9fdf822b33 (diff) | |
| parent | 37de369ba78dd15e40b7fa11b13cea3d2c2ed8d0 (diff) | |
| download | yosys-cbece4af0caebc7f04382f61492e61c84b6acbfd.tar.gz yosys-cbece4af0caebc7f04382f61492e61c84b6acbfd.tar.bz2 yosys-cbece4af0caebc7f04382f61492e61c84b6acbfd.zip | |
Merge pull request #3229 from YosysHQ/micko/sim_date
Add date parameter to enable full date/time and version info
Diffstat (limited to 'tests/verilog')
0 files changed, 0 insertions, 0 deletions