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| author | N. Engelhardt <nak@symbioticeda.com> | 2020-09-28 18:11:18 +0200 |
|---|---|---|
| committer | N. Engelhardt <nak@symbioticeda.com> | 2020-09-28 18:11:18 +0200 |
| commit | 8f1d53e66f62ba140e4cd0d85a3ea69089825c56 (patch) | |
| tree | 6f846582c061e7f305271aef2d342c09ed9aa1c7 /tests/verilog | |
| parent | 08eb0821c9c62ef21e054b6a53a980019bbfa6ca (diff) | |
| download | yosys-8f1d53e66f62ba140e4cd0d85a3ea69089825c56.tar.gz yosys-8f1d53e66f62ba140e4cd0d85a3ea69089825c56.tar.bz2 yosys-8f1d53e66f62ba140e4cd0d85a3ea69089825c56.zip | |
write_verilog: emit intermediate wire for constant values in sensitivity list
Diffstat (limited to 'tests/verilog')
0 files changed, 0 insertions, 0 deletions