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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-04 08:58:50 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-05-04 08:58:50 -0700 |
| commit | 584780d776c92bc91731dbc2710dd8d9a624dc70 (patch) | |
| tree | 5232be5ae42527fa48e9ad5cdfd7113eaab13c57 /tests/verilog/upto.ys | |
| parent | d1c8837572fb343baccff4d766a8aa0bca26aab7 (diff) | |
| parent | b0268b1311c7e70a6726b5ed6285acdefa85f9aa (diff) | |
| download | yosys-584780d776c92bc91731dbc2710dd8d9a624dc70.tar.gz yosys-584780d776c92bc91731dbc2710dd8d9a624dc70.tar.bz2 yosys-584780d776c92bc91731dbc2710dd8d9a624dc70.zip | |
Merge pull request #1996 from boqwxp/rtlil_source_locations
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
Diffstat (limited to 'tests/verilog/upto.ys')
0 files changed, 0 insertions, 0 deletions