verilog: fix sizing of ports with int types in module headers

Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.

1 files changed, 11 insertions, 0 deletions

diff --git a/tests/verilog/port_int_types.ys b/tests/verilog/port_int_types.ys
new file mode 100644
index 000000000..75888e1a8
--- /dev/null
+++ b/tests/verilog/port_int_types.ys
@@ -0,0 +1,11 @@
+read_verilog -sv port_int_types.sv
+equiv_make gold gate_a equiv
+equiv_simple
+equiv_status -assert
+
+design -reset
+
+read_verilog -sv port_int_types.sv
+equiv_make gold gate_b equiv
+equiv_simple
+equiv_status -assert