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author | Zachary Snow <zach@zachjs.com> | 2021-03-01 13:31:25 -0500 |
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committer | Zachary Snow <zach@zachjs.com> | 2021-03-01 13:39:05 -0500 |
commit | 10a6bc9b81d1c2236e80a608778c904aebe54c28 (patch) | |
tree | bc9d0dd7f4893a2a132a7672e5a7f57db1a72726 /tests/verilog/port_int_types.ys | |
parent | 1ec5994100510d6fb9e18ff7234ede496f831a51 (diff) | |
download | yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.tar.gz yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.tar.bz2 yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.zip |
verilog: fix sizing of ports with int types in module headers
Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
Diffstat (limited to 'tests/verilog/port_int_types.ys')
-rw-r--r-- | tests/verilog/port_int_types.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/verilog/port_int_types.ys b/tests/verilog/port_int_types.ys new file mode 100644 index 000000000..75888e1a8 --- /dev/null +++ b/tests/verilog/port_int_types.ys @@ -0,0 +1,11 @@ +read_verilog -sv port_int_types.sv +equiv_make gold gate_a equiv +equiv_simple +equiv_status -assert + +design -reset + +read_verilog -sv port_int_types.sv +equiv_make gold gate_b equiv +equiv_simple +equiv_status -assert |