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| author | Zachary Snow <zach@zachjs.com> | 2021-06-14 15:32:01 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-16 21:48:05 -0400 |
| commit | f2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5 (patch) | |
| tree | d7f7afbb2dd1662c77ba1075a4f8ba6d2055cd03 /tests/verilog/module_end_label.ys | |
| parent | 092f0cb01e91b65d5ecc7c8e45f0eefa30b8c205 (diff) | |
| download | yosys-f2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5.tar.gz yosys-f2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5.tar.bz2 yosys-f2c2d73f36d7aaef90ded549143d1ee0c4d4a9f5.zip | |
sv: fix up end label checking
- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label
Diffstat (limited to 'tests/verilog/module_end_label.ys')
| -rw-r--r-- | tests/verilog/module_end_label.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/verilog/module_end_label.ys b/tests/verilog/module_end_label.ys new file mode 100644 index 000000000..c9e5a13a2 --- /dev/null +++ b/tests/verilog/module_end_label.ys @@ -0,0 +1,15 @@ +logger -expect-no-warnings +read_verilog -sv <<EOF +module correct_name; +localparam X = 1; +endmodule : correct_name +EOF + +design -reset + +logger -expect error "Module name \(correct_name\) and end label \(incorrect_name\) don't match\." 1 +read_verilog -sv <<EOF +module correct_name; +localparam X = 1; +endmodule : incorrect_name +EOF |