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| author | Zachary Snow <zach@zachjs.com> | 2021-08-31 11:45:02 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-08-31 12:34:55 -0600 |
| commit | b2e9717419e9a852f4e64f12891b8e9742900917 (patch) | |
| tree | 3a989a50c1f9beef9068b423f202d4918dcf3d6a /tests/verilog/genfor_decl_no_sv.ys | |
| parent | b20bb653ce0bfe452f8a1ff4a7a9b64262acced3 (diff) | |
| download | yosys-b2e9717419e9a852f4e64f12891b8e9742900917.tar.gz yosys-b2e9717419e9a852f4e64f12891b8e9742900917.tar.bz2 yosys-b2e9717419e9a852f4e64f12891b8e9742900917.zip | |
sv: support declaration in generate for initialization
This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
Diffstat (limited to 'tests/verilog/genfor_decl_no_sv.ys')
| -rw-r--r-- | tests/verilog/genfor_decl_no_sv.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/verilog/genfor_decl_no_sv.ys b/tests/verilog/genfor_decl_no_sv.ys new file mode 100644 index 000000000..124a27c28 --- /dev/null +++ b/tests/verilog/genfor_decl_no_sv.ys @@ -0,0 +1,7 @@ +logger -expect error "Generate for loop inline variable declaration is only supported in SystemVerilog mode!" 1 +read_verilog <<EOT +module top; + for (genvar i = 1; i < 10; i = i + 1) + wire x; +endmodule +EOT |