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author | Zachary Snow <zach@zachjs.com> | 2021-02-21 14:45:21 -0500 |
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committer | Zachary Snow <zach@zachjs.com> | 2021-02-21 15:44:43 -0500 |
commit | b6af90fe20bc92631061c48c328f3c6e4760e4df (patch) | |
tree | 9c8fb14f37ae5c4339fd550b7c8322e70c4cf940 /tests/verilog/func_arg_mismatch_2.ys | |
parent | 127484e675538fbaeca1f6e53ba264a1f02e9cf6 (diff) | |
download | yosys-b6af90fe20bc92631061c48c328f3c6e4760e4df.tar.gz yosys-b6af90fe20bc92631061c48c328f3c6e4760e4df.tar.bz2 yosys-b6af90fe20bc92631061c48c328f3c6e4760e4df.zip |
verilog: fix sizing of constant args for tasks/functions
- Simplify synthetic localparams for normal calls to update their width
- This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
- `eval_const_function` never correctly handled this, but the issue
was not exposed in the existing tests until the recent change to
always attempt constant function evaluation when all-const args
are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
Diffstat (limited to 'tests/verilog/func_arg_mismatch_2.ys')
-rw-r--r-- | tests/verilog/func_arg_mismatch_2.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/verilog/func_arg_mismatch_2.ys b/tests/verilog/func_arg_mismatch_2.ys new file mode 100644 index 000000000..c2c29c1fb --- /dev/null +++ b/tests/verilog/func_arg_mismatch_2.ys @@ -0,0 +1,12 @@ +logger -expect error "Incompatible re-declaration of constant function wire" 1 +read_verilog -sv <<EOT +module top; + function automatic integer f; + input [0:0] inp; + integer inp; + f = inp; + endfunction + integer x; + initial x = f(0); +endmodule +EOT |