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author | N. Engelhardt <nak@symbioticeda.com> | 2020-09-28 18:12:40 +0200 |
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committer | N. Engelhardt <nak@symbioticeda.com> | 2020-09-28 18:16:08 +0200 |
commit | dc4a6176945618a40960fdd79ecfa2a8ef104487 (patch) | |
tree | 62fa70743a0aa635dc4cbc52a250831e2926175c /tests/verilog/const_sr.ys | |
parent | 8f1d53e66f62ba140e4cd0d85a3ea69089825c56 (diff) | |
download | yosys-dc4a6176945618a40960fdd79ecfa2a8ef104487.tar.gz yosys-dc4a6176945618a40960fdd79ecfa2a8ef104487.tar.bz2 yosys-dc4a6176945618a40960fdd79ecfa2a8ef104487.zip |
add tests
Diffstat (limited to 'tests/verilog/const_sr.ys')
-rw-r--r-- | tests/verilog/const_sr.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/verilog/const_sr.ys b/tests/verilog/const_sr.ys new file mode 100644 index 000000000..c1406b0a0 --- /dev/null +++ b/tests/verilog/const_sr.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module test ( + input clk, rst, d, + output reg q +); +wire nop = 1'h0; +always @(posedge clk, posedge nop, posedge rst) begin + if (rst) q <= 1'b0; + else if (nop) q <= 1'b1; + else q <= d; +end +endmodule +EOT +prep -top test +write_verilog const_sr.v +design -stash gold +read_verilog const_sr.v +prep -top test +design -stash gate +design -copy-from gold -as gold A:top +design -copy-from gate -as gate A:top +miter -equiv -flatten -make_assert gold gate miter +prep -top miter +clk2fflogic +sat -set-init-zero -tempinduct -prove-asserts -verify |