diff options
author | Zachary Snow <zach@zachjs.com> | 2022-01-06 22:04:00 -0700 |
---|---|---|
committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-01-07 22:53:22 -0700 |
commit | aa35f24290b0d7339860c8c8a6145703425fa154 (patch) | |
tree | afee581c29c4c6e483138c7693e97e88afad167e /tests/verilog/always_comb_latch_3.ys | |
parent | 828e85068f8dd52a508e4cbb84deea0e621aa038 (diff) | |
download | yosys-aa35f24290b0d7339860c8c8a6145703425fa154.tar.gz yosys-aa35f24290b0d7339860c8c8a6145703425fa154.tar.bz2 yosys-aa35f24290b0d7339860c8c8a6145703425fa154.zip |
sv: auto add nosync to certain always_comb local vars
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
Diffstat (limited to 'tests/verilog/always_comb_latch_3.ys')
-rw-r--r-- | tests/verilog/always_comb_latch_3.ys | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/tests/verilog/always_comb_latch_3.ys b/tests/verilog/always_comb_latch_3.ys new file mode 100644 index 000000000..b9b028ac7 --- /dev/null +++ b/tests/verilog/always_comb_latch_3.ys @@ -0,0 +1,20 @@ +read_verilog -sv <<EOF +module top; +logic x; +logic z; +assign z = 1'b1; +always_comb begin + logic y; + case (x) + 1'b0: + y = 1; + endcase + if (z) + x = y; + else + x = 1'b0; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process" 1 +proc |