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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-03 12:30:37 +0200 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-09 18:47:08 +0100 |
| commit | fecd3aa2b15a20fc72d790b2437ee016ae879c14 (patch) | |
| tree | 6a880c886961cf36feb69a5de3099d0a9b26e249 /tests/various | |
| parent | d105e2f03f259e4f2be3d6d9ba970565d8422b87 (diff) | |
| download | yosys-fecd3aa2b15a20fc72d790b2437ee016ae879c14.tar.gz yosys-fecd3aa2b15a20fc72d790b2437ee016ae879c14.tar.bz2 yosys-fecd3aa2b15a20fc72d790b2437ee016ae879c14.zip | |
Merge pull request #1147 from YosysHQ/clifford/fix1144
Improve specify dummy parser
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/specify.v | 11 | ||||
| -rw-r--r-- | tests/various/specify.ys | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index afc421da8..5d44d78f7 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,9 +7,11 @@ module test ( if (EN) Q <= D; specify - if (EN) (CLK *> (Q : D)) = (1, 2:3:4); +`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS + if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); +`endif endspecify endmodule @@ -28,3 +30,10 @@ module test2 ( (B => Q) = 1.5; endspecify endmodule + +module issue01144(input clk, d, output q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a5ca07219..00597e1e2 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -54,3 +54,5 @@ equiv_struct equiv_induct -seq 5 equiv_status -assert design -reset + +read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v |