diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:36:37 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 13:36:37 -0700 |
commit | bdb5e0f29c3e913fb4e701317105363064b9a7d3 (patch) | |
tree | cc3db403a7be2c5fa909ebdb89520464ee42e9e0 /tests/various | |
parent | 4937917cd8fb351740ffd936ea8a227795872775 (diff) | |
download | yosys-bdb5e0f29c3e913fb4e701317105363064b9a7d3.tar.gz yosys-bdb5e0f29c3e913fb4e701317105363064b9a7d3.tar.bz2 yosys-bdb5e0f29c3e913fb4e701317105363064b9a7d3.zip |
Cope with presence of reset muxes too
Diffstat (limited to 'tests/various')
-rw-r--r-- | tests/various/peepopt.ys | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 8dce679ff..886c8cd9d 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -110,3 +110,42 @@ design -load postopt select -assert-count 1 t:$dff r:WIDTH=5 %i select -assert-count 1 t:$mux r:WIDTH=5 %i select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i; +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT +module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o); + always @(posedge clk) begin + if (ce) o <= i; + if (!rstn) o <= 4'b1111; + end +endmodule +EOT + +proc +equiv_opt -assert peepopt +design -load postopt +wreduce +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 2 t:$mux +select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D |