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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:07:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-11 00:07:17 -0700 |
| commit | 580faae8ad608981ef6ef6a99ca6b771dc0368ae (patch) | |
| tree | 711e90497a9fdb0fded9c83d733f71880d8e1051 /tests/various | |
| parent | 97e1520b13231c8170cec73774eee7a22c5dc065 (diff) | |
| download | yosys-580faae8ad608981ef6ef6a99ca6b771dc0368ae.tar.gz yosys-580faae8ad608981ef6ef6a99ca6b771dc0368ae.tar.bz2 yosys-580faae8ad608981ef6ef6a99ca6b771dc0368ae.zip | |
Add unsigned case
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/peepopt.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 33555264d..e930015a4 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -49,6 +49,23 @@ select -assert-count 0 t:* design -reset read_verilog <<EOT +module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); + always @(posedge clk) if (ce) o <= i; +endmodule +EOT + +prep -nokeepdc +equiv_opt -assert peepopt +design -load postopt +clean +select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$mux r:WIDTH=2 %i +select -assert-count 0 t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog <<EOT module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); always @(posedge clk) if (ce) o <= i; endmodule |