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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 16:33:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 16:33:18 -0700 |
| commit | 14d72c39c385bba3005085815a0d66989a437eff (patch) | |
| tree | 243f876a7c098c24267ac77653824fbe187d5cfd /tests/various | |
| parent | 3a49aa6b4a707f558ec378a25d28c3e0d914cfac (diff) | |
| download | yosys-14d72c39c385bba3005085815a0d66989a437eff.tar.gz yosys-14d72c39c385bba3005085815a0d66989a437eff.tar.bz2 yosys-14d72c39c385bba3005085815a0d66989a437eff.zip | |
Revert "Make one check $shift(x)? only; change testcase to be 8b"
This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80.
Diffstat (limited to 'tests/various')
| -rw-r--r-- | tests/various/peepopt.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 886c8cd9d..abee9cc0a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D design -reset read_verilog <<EOT module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); -assign y = 1'b1 >> (w * (8'b110)); +assign y = 1'b1 >> (w * (3'b110)); endmodule EOT @@ -25,7 +25,7 @@ equiv_opt -assert peepopt design -load postopt clean select -assert-count 1 t:$shr -select -assert-count 0 t:$mul +select -assert-count 1 t:$mul select -assert-count 0 t:$shr t:$mul %% t:* %D #################### |