diff options
author | David Shah <dave@ds0.me> | 2019-11-21 21:06:28 +0000 |
---|---|---|
committer | David Shah <dave@ds0.me> | 2019-11-21 21:06:28 +0000 |
commit | 49b670ca38988bcce453125166528b32e16f7bb4 (patch) | |
tree | 283a6d0b736723d08a645006c28ee90047045412 /tests/various/svalways.sh | |
parent | ca99b1ee8dca6d49d79576e19d35111b4ad5ea45 (diff) | |
download | yosys-49b670ca38988bcce453125166528b32e16f7bb4.tar.gz yosys-49b670ca38988bcce453125166528b32e16f7bb4.tar.bz2 yosys-49b670ca38988bcce453125166528b32e16f7bb4.zip |
sv: Add tests for SV always types
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/various/svalways.sh')
-rwxr-xr-x | tests/various/svalways.sh | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/tests/various/svalways.sh b/tests/various/svalways.sh new file mode 100755 index 000000000..2cc09f801 --- /dev/null +++ b/tests/various/svalways.sh @@ -0,0 +1,63 @@ +#!/bin/bash + +trap 'echo "ERROR in svalways.sh" >&2; exit 1' ERR + +# Good case +../../yosys -f "verilog -sv" -qp proc - <<EOT +module top(input clk, en, d, output reg p, q, r); + +always_ff @(posedge clk) + p <= d; + +always_comb + q = ~d; + +always_latch + if (en) r = d; + +endmodule +EOT + +# Incorrect always_comb syntax +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input d, output reg q); + +always_comb @(d) + q = ~d; + +endmodule +EOT +) 2>&1 | grep -F "<stdin>:3: ERROR: syntax error, unexpected '@'" > /dev/null + +# Incorrect use of always_comb +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_comb + if (en) q = d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null + +# Incorrect use of always_latch +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_latch + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null + +# Incorrect use of always_ff +((../../yosys -f "verilog -sv" -qp proc -|| true) <<EOT +module top(input en, d, output reg q); + +always_ff @(*) + q = !d; + +endmodule +EOT +) 2>&1 | grep -F "ERROR: Found non edge/level sensitive event in always_ff process" > /dev/null |