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author | Clifford Wolf <clifford@clifford.at> | 2019-07-03 11:25:05 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2019-07-03 11:25:05 +0200 |
commit | 1f173210ebbf2cd5b5714e351ed40b6141d90b14 (patch) | |
tree | d50bdfa62b6d7743c0c5b4b7a0f8b05778a2552a /tests/various/specify.ys | |
parent | ba365679082cff2b9879eef5349bfdf2b5291449 (diff) | |
download | yosys-1f173210ebbf2cd5b5714e351ed40b6141d90b14.tar.gz yosys-1f173210ebbf2cd5b5714e351ed40b6141d90b14.tar.bz2 yosys-1f173210ebbf2cd5b5714e351ed40b6141d90b14.zip |
Fix tests/various/specify.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/various/specify.ys')
-rw-r--r-- | tests/various/specify.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a2b6038e4..00597e1e2 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,4 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog specify.v +read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v |