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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 12:16:01 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:42:04 -0800 |
| commit | 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a (patch) | |
| tree | c94c86d18749a16b405545aa95718254a350513a /tests/various/specify.v | |
| parent | cb7bc6a12fee1d948b7f91fd37f326dbd4f5ca47 (diff) | |
| download | yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.tar.gz yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.tar.bz2 yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.zip | |
verilog: fix $specify3 check
Diffstat (limited to 'tests/various/specify.v')
| -rw-r--r-- | tests/various/specify.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index 5d44d78f7..e4dd132f1 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -37,3 +37,10 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test3(input clk, input [1:0] d, output [1:0] q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule |