diff options
author | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:35:26 -0700 |
---|---|---|
committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-03 15:35:26 -0700 |
commit | 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 (patch) | |
tree | d32f3475fba92e1f529e1117680c651aff0eba36 /tests/various/specify.v | |
parent | d9c4644e88b916d1eadfd401abf297c0995b6462 (diff) | |
download | yosys-09841c2ac1f36d06faada27093a2cf0cdfb6cb42.tar.gz yosys-09841c2ac1f36d06faada27093a2cf0cdfb6cb42.tar.bz2 yosys-09841c2ac1f36d06faada27093a2cf0cdfb6cb42.zip |
Add quick-and-dirty specify tests
Diffstat (limited to 'tests/various/specify.v')
-rw-r--r-- | tests/various/specify.v | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v new file mode 100644 index 000000000..aea0d0fc5 --- /dev/null +++ b/tests/various/specify.v @@ -0,0 +1,28 @@ +module test ( + input EN, CLK, + input [3:0] D, + output reg [3:0] Q +); + always @(posedge CLK) + if (EN) Q <= D; + + specify + if (EN) (CLK *> (Q : D)) = (1, 2:3:4); + $setup(D, posedge CLK &&& EN, 5); + $hold(posedge CLK, D &&& EN, 6); + endspecify +endmodule + +module test2 ( + input A, B, + output Q +); + xor (Q, A, B); + specify + //specparam T_rise = 1; + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); + endspecify +endmodule |