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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:05:41 -0700 |
| commit | 052060f10906ca859d2313b86800e110bd34b79f (patch) | |
| tree | 356107e4270feb84046b984a98e0874f1436b2d9 /tests/various/specify.v | |
| parent | 35fd9b04731d3bc944e1471b96668ef0cf7b51f1 (diff) | |
| parent | bb2144ae733f1a2c5e629a8251bfbdcc15559aa4 (diff) | |
| download | yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.gz yosys-052060f10906ca859d2313b86800e110bd34b79f.tar.bz2 yosys-052060f10906ca859d2313b86800e110bd34b79f.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/various/specify.v')
| -rw-r--r-- | tests/various/specify.v | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/tests/various/specify.v b/tests/various/specify.v index afc421da8..5d44d78f7 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,9 +7,11 @@ module test ( if (EN) Q <= D; specify - if (EN) (CLK *> (Q : D)) = (1, 2:3:4); +`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS + if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); +`endif endspecify endmodule @@ -28,3 +30,10 @@ module test2 ( (B => Q) = 1.5; endspecify endmodule + +module issue01144(input clk, d, output q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule |