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author | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
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committer | Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com> | 2019-06-27 12:11:47 +0200 |
commit | 0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7 (patch) | |
tree | 9ed03b8345847046143161c3a63b8fa599393da2 /tests/various/shregmap.v | |
parent | 2454ad99bf49afe752d6fd1c1567f59ee9e26736 (diff) | |
parent | 0d2b87e3ed9bacae7d44d27a4712e56ca03c8dd3 (diff) | |
download | yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.gz yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.tar.bz2 yosys-0f32cb4e0af85e16a90ae274cf7c9fee6fbd2ad7.zip |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'tests/various/shregmap.v')
-rw-r--r-- | tests/various/shregmap.v | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v new file mode 100644 index 000000000..604c2c976 --- /dev/null +++ b/tests/various/shregmap.v @@ -0,0 +1,48 @@ +module shregmap_static_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module $__SHREG_DFF_P_(input C, D, output Q); +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +always @(posedge C) + r <= { r[DEPTH-2:0], D }; +assign Q = r[DEPTH-1]; +endmodule + +module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule |