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| author | Udi Finkelstein <github@udifink.com> | 2018-06-05 12:15:59 +0300 |
|---|---|---|
| committer | Unknown <github@udifink.com> | 2018-06-05 18:00:06 +0300 |
| commit | 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 (patch) | |
| tree | 68d7f6d234399e075af592d16d4f9120c714be25 /tests/various/reg_wire_error.ys | |
| parent | 2b9c75f8e372f6886e073743d1df11bcd1c58281 (diff) | |
| download | yosys-80d9d15f1c4b73ee73172b06fd2c8c55703aea54.tar.gz yosys-80d9d15f1c4b73ee73172b06fd2c8c55703aea54.tar.bz2 yosys-80d9d15f1c4b73ee73172b06fd2c8c55703aea54.zip | |
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
Diffstat (limited to 'tests/various/reg_wire_error.ys')
| -rw-r--r-- | tests/various/reg_wire_error.ys | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys new file mode 100644 index 000000000..b9d03155d --- /dev/null +++ b/tests/various/reg_wire_error.ys @@ -0,0 +1 @@ +read_verilog -sv reg_wire_error.sv |