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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:45:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 11:45:53 -0700 |
| commit | 6ec816098153c733b97410ebc6aef166db8affd8 (patch) | |
| tree | f8eb498e163c4431739d25c0c01fa4d1c05a7b83 /tests/various/muxpack.v | |
| parent | 641b86d25f5baa898bf5fca3d1a8f2fd4f5954e6 (diff) | |
| download | yosys-6ec816098153c733b97410ebc6aef166db8affd8.tar.gz yosys-6ec816098153c733b97410ebc6aef166db8affd8.tar.bz2 yosys-6ec816098153c733b97410ebc6aef166db8affd8.zip | |
Add more muxpack tests, with overlapping entries
Diffstat (limited to 'tests/various/muxpack.v')
| -rw-r--r-- | tests/various/muxpack.v | 55 |
1 files changed, 54 insertions, 1 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 3a1086dbf..7a658d754 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -187,7 +187,9 @@ module case_nonexclusive_select ( ); always @* begin case (x) - 0, 2: o = b; + //0, 2: o = b; + 0: o = b; + 2: o = b; 1: o = c; default: begin o = a; @@ -197,3 +199,54 @@ module case_nonexclusive_select ( endcase end endmodule + +module case_nonoverlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule + +module case_overlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 2: o = 1'b1; // Overlaps with previous $pmux + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule |