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| author | clairexen <claire@symbioticeda.com> | 2020-07-15 11:49:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-15 11:49:09 +0200 |
| commit | 021ce8e59646ed9a6dff4447e11cceae9d3e615c (patch) | |
| tree | 175394ccfbc749c48f3ac0e057db630c7e78d566 /tests/various/logic_param_simple.ys | |
| parent | 61a7ec4768a3d0d0c8875bb4d9b6160f8697c0d6 (diff) | |
| parent | 02c071888b4b2a26db5653609bb60e6c3f5c366f (diff) | |
| download | yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.tar.gz yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.tar.bz2 yosys-021ce8e59646ed9a6dff4447e11cceae9d3e615c.zip | |
Merge pull request #2257 from antmicro/fix-conflicts
Restore #2203 and #2244 and fix parser conflicts
Diffstat (limited to 'tests/various/logic_param_simple.ys')
| -rw-r--r-- | tests/various/logic_param_simple.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys new file mode 100644 index 000000000..968564080 --- /dev/null +++ b/tests/various/logic_param_simple.ys @@ -0,0 +1,9 @@ +read_verilog -sv <<EOT +module test_logic_param(); +parameter logic a = 0; +parameter logic [31:0] e = 0; +parameter logic signed b = 0; +parameter logic unsigned c = 0; +parameter logic unsigned [31:0] d = 0; +endmodule +EOT |