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author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-07-06 09:05:34 +0200 |
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committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-07-06 09:18:48 +0200 |
commit | b422f2e4d0b8d5bfa97913d6b9dee488b59fc405 (patch) | |
tree | 26583044638503a679fae71bf057505cecaa07d6 /tests/various/integer_real_bad_syntax.ys | |
parent | 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15 (diff) | |
download | yosys-b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.tar.gz yosys-b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.tar.bz2 yosys-b422f2e4d0b8d5bfa97913d6b9dee488b59fc405.zip |
Add logic param and integer bad syntax tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'tests/various/integer_real_bad_syntax.ys')
-rw-r--r-- | tests/various/integer_real_bad_syntax.ys | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys new file mode 100644 index 000000000..942d8de77 --- /dev/null +++ b/tests/various/integer_real_bad_syntax.ys @@ -0,0 +1,6 @@ +logger -expect error "syntax error, unexpected TOK_REAL" 1 +read_verilog -sv <<EOT +module test_integer_real(); +parameter integer real a = 0; +endmodule +EOT |