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authorEddie Hung <eddieh@ece.ubc.ca>2019-02-26 13:16:03 -0800
committerEddie Hung <eddieh@ece.ubc.ca>2019-02-26 13:16:03 -0800
commitf7c7003a193361285ba59d1315c1e7c26c4c52f1 (patch)
tree1b5ef37eb342883aec8b3b306cd410a660311d21 /tests/various/hierarchy.sh
parentdfb23a79dd0e2ffbe4f058eadb552d8194540eef (diff)
parent7a40294e93490fa462343244b1e2881c3c249c3f (diff)
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Merge remote-tracking branch 'origin/master' into xaig
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+#!/usr/bin/env bash
+# Simple test of hierarchy -auto-top.
+
+set -e
+
+echo -n " TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
+ read_verilog << EOV
+ module TOP(a, y);
+ input a;
+ output [31:0] y;
+
+ aoi12 p [31:0] (a, y);
+ endmodule
+
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY
+
+echo -n " TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
+ read_verilog << EOV
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+
+ module TOP(a, y);
+ input a;
+ output [31:0] y;
+
+ aoi12 foo (a, y);
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY
+
+echo -n " no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
+ read_verilog << EOV
+ module aoi12(a, y);
+ input a;
+ output y;
+ assign y = ~a;
+ endmodule
+
+ module noTop(a, y);
+ input a;
+ output [31:0] y;
+ endmodule
+ EOV
+ hierarchy -auto-top
+EOY