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| author | Zachary Snow <zach@zachjs.com> | 2021-02-12 14:25:34 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-02-12 14:43:42 -0500 |
| commit | 8de2e863af4233aca0a0ca0eef4477d216f7a227 (patch) | |
| tree | 4854ab4fb9acbee14151db50dd09795825954bbd /tests/various/fib_tern.ys | |
| parent | 9f7cd10c9887df7a8fb8e0d587955d5a03b60c52 (diff) | |
| download | yosys-8de2e863af4233aca0a0ca0eef4477d216f7a227.tar.gz yosys-8de2e863af4233aca0a0ca0eef4477d216f7a227.tar.bz2 yosys-8de2e863af4233aca0a0ca0eef4477d216f7a227.zip | |
verilog: support recursive functions using ternary expressions
This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
Diffstat (limited to 'tests/various/fib_tern.ys')
| -rw-r--r-- | tests/various/fib_tern.ys | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/various/fib_tern.ys b/tests/various/fib_tern.ys new file mode 100644 index 000000000..e5bf186e1 --- /dev/null +++ b/tests/various/fib_tern.ys @@ -0,0 +1,6 @@ +read_verilog fib_tern.v +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert |