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authorEddie Hung <eddie@fpgeh.com>2020-04-16 12:48:40 -0700
committerEddie Hung <eddie@fpgeh.com>2020-04-16 12:48:40 -0700
commit9eace8f36032665394e582a60fc58be0a7c9303b (patch)
treec76f0cc995b9ee61fa1139e185c5319ae9a35e08 /tests/various/design1.ys
parentdac5adde12c585f5e0552f776ae0a5ab05e995c9 (diff)
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design: add test
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-rw-r--r--tests/various/design1.ys9
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/design1.ys b/tests/various/design1.ys
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+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -delete foo