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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:48:40 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 12:48:40 -0700 |
commit | 9eace8f36032665394e582a60fc58be0a7c9303b (patch) | |
tree | c76f0cc995b9ee61fa1139e185c5319ae9a35e08 /tests/various/design1.ys | |
parent | dac5adde12c585f5e0552f776ae0a5ab05e995c9 (diff) | |
download | yosys-9eace8f36032665394e582a60fc58be0a7c9303b.tar.gz yosys-9eace8f36032665394e582a60fc58be0a7c9303b.tar.bz2 yosys-9eace8f36032665394e582a60fc58be0a7c9303b.zip |
design: add test
Diffstat (limited to 'tests/various/design1.ys')
-rw-r--r-- | tests/various/design1.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/design1.ys b/tests/various/design1.ys new file mode 100644 index 000000000..f13ad8171 --- /dev/null +++ b/tests/various/design1.ys @@ -0,0 +1,9 @@ +read_verilog <<EOT +module top(input i, output o); +assign o = i; +endmodule +EOT +design -stash foo +design -delete foo +logger -expect error "No saved design 'foo' found!" 1 +design -delete foo |