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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-14 10:34:23 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-16 08:05:18 -0700 |
commit | e8a841467f4ddd85acfcfbcda2cd28d43e75341a (patch) | |
tree | 82e6188f082efcf2a8db0ea9c74a85a1f29ffc5f /tests/various/design.ys | |
parent | a9ec0defb9a1d38690f772f1b7d80562df8ca2ce (diff) | |
download | yosys-e8a841467f4ddd85acfcfbcda2cd28d43e75341a.tar.gz yosys-e8a841467f4ddd85acfcfbcda2cd28d43e75341a.tar.bz2 yosys-e8a841467f4ddd85acfcfbcda2cd28d43e75341a.zip |
tests: add design -delete tests
Diffstat (limited to 'tests/various/design.ys')
-rw-r--r-- | tests/various/design.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/design.ys b/tests/various/design.ys new file mode 100644 index 000000000..f13ad8171 --- /dev/null +++ b/tests/various/design.ys @@ -0,0 +1,9 @@ +read_verilog <<EOT +module top(input i, output o); +assign o = i; +endmodule +EOT +design -stash foo +design -delete foo +logger -expect error "No saved design 'foo' found!" 1 +design -delete foo |