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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 10:07:58 -0700 |
| commit | 60aa8049157eb4f0417022182aeb8c1581efe404 (patch) | |
| tree | c4c14d7ebe03463457e55491a570fb4e76dc13b7 /tests/various/attrib07_func_call.v | |
| parent | ae11156c90eec958cd9ab631a28c41eccc105e56 (diff) | |
| download | yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.gz yosys-60aa8049157eb4f0417022182aeb8c1581efe404.tar.bz2 yosys-60aa8049157eb4f0417022182aeb8c1581efe404.zip | |
tests: fix some test warnings
Diffstat (limited to 'tests/various/attrib07_func_call.v')
| -rw-r--r-- | tests/various/attrib07_func_call.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v index f55ef2316..8c9fb2926 100644 --- a/tests/various/attrib07_func_call.v +++ b/tests/various/attrib07_func_call.v @@ -11,7 +11,7 @@ module foo(clk, rst, inp_a, inp_b, out); input wire rst; input wire [7:0] inp_a; input wire [7:0] inp_b; - output wire [7:0] out; + output reg [7:0] out; always @(posedge clk) if (rst) out <= 0; |