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| author | Maciej Kurc <mkurc@antmicro.com> | 2019-06-04 10:42:42 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2019-06-04 10:42:42 +0200 |
| commit | b79bd5b3ca086718e308c75cbece0b07bbe48733 (patch) | |
| tree | cf5ea057804392bef613a5c86046ce2b35700c28 /tests/various/attrib05_port_conn.ys | |
| parent | 5739cf52650ccb3627868d9c9d7e02888efad12b (diff) | |
| download | yosys-b79bd5b3ca086718e308c75cbece0b07bbe48733.tar.gz yosys-b79bd5b3ca086718e308c75cbece0b07bbe48733.tar.bz2 yosys-b79bd5b3ca086718e308c75cbece0b07bbe48733.zip | |
Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'tests/various/attrib05_port_conn.ys')
| -rw-r--r-- | tests/various/attrib05_port_conn.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/various/attrib05_port_conn.ys b/tests/various/attrib05_port_conn.ys new file mode 100644 index 000000000..27a016733 --- /dev/null +++ b/tests/various/attrib05_port_conn.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib05_port_conn.v |