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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 17:05:14 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 17:05:14 -0800 |
| commit | 1cc106452fb25d082ca9491c24df97cc51d4b992 (patch) | |
| tree | 5d63c1c18872bf65aad6bb5bfb7fcb5670d7c313 /tests/various/abc9.v | |
| parent | 90c5ca330c5e6c8eb45ad0b755b0049a34dc7534 (diff) | |
| download | yosys-1cc106452fb25d082ca9491c24df97cc51d4b992.tar.gz yosys-1cc106452fb25d082ca9491c24df97cc51d4b992.tar.bz2 yosys-1cc106452fb25d082ca9491c24df97cc51d4b992.zip | |
Add a equiv test too
Diffstat (limited to 'tests/various/abc9.v')
| -rw-r--r-- | tests/various/abc9.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 30ebd4e26..e53dcdb21 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -9,3 +9,10 @@ wire w; unknown u(~i, w); unknown2 u2(w, o); endmodule + +module abc9_test031(input clk, d, r, output reg q); +initial q = 1'b0; +always @(negedge clk or negedge r) + if (r) q <= 1'b0; + else q <= d; +endmodule |