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author | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
commit | 136842b1ef18b850b518705ff3e6df3958f28e0c (patch) | |
tree | abcdddaf53bafd5e34e9aa278ffbe3d001b60cc4 /tests/various/abc9.v | |
parent | 705e520a527864dc32f1934bb4b2b94d75f8f0ec (diff) | |
parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
download | yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.gz yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.bz2 yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.zip |
Merge branch 'master' into eddie/submod_po
Diffstat (limited to 'tests/various/abc9.v')
-rw-r--r-- | tests/various/abc9.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 30ebd4e26..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -9,3 +9,10 @@ wire w; unknown u(~i, w); unknown2 u2(w, o); endmodule + +module abc9_test032(input clk, d, r, output reg q); +initial q = 1'b0; +always @(negedge clk or negedge r) + if (!r) q <= 1'b0; + else q <= d; +endmodule |