diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:06:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:06:40 +0100 |
| commit | 81b3f52519d388f252405fa7cc7472ca9e51bc49 (patch) | |
| tree | 26d1faee61bcac2276307c8919b20ca493dfedd2 /tests/techmap/mem_simple_4x1_uut.v | |
| parent | 79f8944811cba40ca0f3bda98ab951395d24fa0b (diff) | |
| download | yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.tar.gz yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.tar.bz2 yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.zip | |
Added tests/techmap/mem_simple_4x1
Diffstat (limited to 'tests/techmap/mem_simple_4x1_uut.v')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_uut.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/techmap/mem_simple_4x1_uut.v b/tests/techmap/mem_simple_4x1_uut.v new file mode 100644 index 000000000..8d4614595 --- /dev/null +++ b/tests/techmap/mem_simple_4x1_uut.v @@ -0,0 +1,15 @@ +module uut (clk, rst, out, counter); + +input clk, rst; +output reg [7:0] out; +output reg [4:0] counter; + +reg [7:0] memory [0:19]; + +always @(posedge clk) begin + counter <= rst || counter == 19 ? 0 : counter+1; + memory[counter] <= counter; + out <= memory[counter]; +end + +endmodule |