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author | Marcin KoĆcielnicki <koriakin@0x04.net> | 2019-08-28 14:58:14 +0000 |
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committer | Marcin KoĆcielnicki <koriakin@0x04.net> | 2019-09-19 04:02:48 +0200 |
commit | c9f9518de4af34b2539d230c0894b04d174b755d (patch) | |
tree | c4c4062344d55f7ef4935ef6f68475b7f233722f /tests/techmap/extractinv.ys | |
parent | 70c607d7dde23b709ffd36c47680cddcc4666fcd (diff) | |
download | yosys-c9f9518de4af34b2539d230c0894b04d174b755d.tar.gz yosys-c9f9518de4af34b2539d230c0894b04d174b755d.tar.bz2 yosys-c9f9518de4af34b2539d230c0894b04d174b755d.zip |
Added extractinv pass
Diffstat (limited to 'tests/techmap/extractinv.ys')
-rw-r--r-- | tests/techmap/extractinv.ys | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys new file mode 100644 index 000000000..6146f829a --- /dev/null +++ b/tests/techmap/extractinv.ys @@ -0,0 +1,41 @@ +read_verilog << EOT + +module ff4(...); +parameter [0:0] CLK_INV = 1'b0; +parameter [3:0] DATA_INV = 4'b0000; +(* invertible_pin = "CLK_INV" *) +input clk; +(* invertible_pin = "DATA_INV" *) +input [3:0] d; +output [3:0] q; +endmodule + +module inv(...); +output o; +input i; +endmodule + +module top(...); +input d0, d1, d2, d3; +input clk; +output q; +ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q)); +endmodule + +EOT + +extractinv -inv inv o:i +clean + +select -assert-count 2 top/t:inv +select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i + +select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i +select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i +select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i + +select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i +select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i +select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i |