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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-07 14:22:04 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-09 18:12:47 +0200 |
| commit | 03e28f7ab43116cd4f7fed0e37647637a4d8eda0 (patch) | |
| tree | bcbc9cdec25bf44fb89097940743645735a4cfb9 /tests/techmap/dfflegalize_adff_init.ys | |
| parent | e9c2c1b7175604acd4285800c441c4bd1d676f9d (diff) | |
| download | yosys-03e28f7ab43116cd4f7fed0e37647637a4d8eda0.tar.gz yosys-03e28f7ab43116cd4f7fed0e37647637a4d8eda0.tar.bz2 yosys-03e28f7ab43116cd4f7fed0e37647637a4d8eda0.zip | |
clk2fflogic: Consistently treat async control signals as negative hold.
This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
Diffstat (limited to 'tests/techmap/dfflegalize_adff_init.ys')
| -rw-r--r-- | tests/techmap/dfflegalize_adff_init.ys | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/techmap/dfflegalize_adff_init.ys b/tests/techmap/dfflegalize_adff_init.ys index 92f249815..a10161701 100644 --- a/tests/techmap/dfflegalize_adff_init.ys +++ b/tests/techmap/dfflegalize_adff_init.ys @@ -45,10 +45,10 @@ equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0 equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1 equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1 -#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 -#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 -#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 -#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0 +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1 # Convert everything to ADFFs. |