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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-05 21:01:20 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-05 21:01:20 +0200 |
| commit | c1ed1c28be9bd9880cc036d13f43294bf257788b (patch) | |
| tree | 4ce011ac29f69cfdb1d94a1d71aa5170ea79acdc /tests/techmap/bug2332.ys | |
| parent | c39ebe6ae0e41cf9a84da852fa3cf9f71937a9b2 (diff) | |
| download | yosys-c1ed1c28be9bd9880cc036d13f43294bf257788b.tar.gz yosys-c1ed1c28be9bd9880cc036d13f43294bf257788b.tar.bz2 yosys-c1ed1c28be9bd9880cc036d13f43294bf257788b.zip | |
peeopt.shiftmul: Add a signedness check.
Fixes #2332.
Diffstat (limited to 'tests/techmap/bug2332.ys')
| -rw-r--r-- | tests/techmap/bug2332.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/techmap/bug2332.ys b/tests/techmap/bug2332.ys new file mode 100644 index 000000000..ed6b35eb2 --- /dev/null +++ b/tests/techmap/bug2332.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module top(input [31:0] a, input signed [2:0] x, output [2:0] o); + +wire [5:0] t = x * 3; +assign o = a >> t; + +endmodule +EOT + +wreduce +equiv_opt -assert peepopt |